`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/10/13 15:40:08
// Design Name: 
// Module Name: bram_ctl
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module bram_ctl(
        input                   clk_bram,
        input                   rstb,
		output         [31:0]   addrb,
		input          [31:0]   doutb,			
		output     reg [31:0]   dinb ,
        output     reg [31:0]   bram_data0 ,
        output     reg [31:0]   bram_data1 ,
        output     reg [31:0]   bram_data2 ,
        output     reg [31:0]   bram_data3 ,
        output     reg [31:0]   bram_data4 ,
        output     reg [31:0]   bram_data5 ,
        output     reg [31:0]   bram_data6 ,
        output     reg [31:0]   bram_data7 ,
        
		output     reg [3:0]    we,
        output     reg [31:0]   addrbRead,
        output     reg [0:0]    rdState,
        input                   readEnVio,
        input          [31:0]  AddrEndValueVio //控制写的地址范围
);



localparam MAX_ADDR =  8'd32;

(* keep = "true" *) reg [32:0]   bram_data[9:0];
(* keep = "true" *) reg          rd_done;
reg  [0:0] readEnReg1;	//对readEnVio延迟一个clk

// reg  [31:0]addrbRead;	//读数据地址


always@(posedge clk_bram)begin
    if(~rstb)begin
        readEnReg1 <= 1'b0;	
    end 
    else begin
        readEnReg1 <= readEnVio;		
    end		
end	

always@(posedge clk_bram)begin
    if(~rstb)begin
        rdState    		<= 1'b0;
        addrbRead[31:0] <= 32'd0;
        rd_done         <= 1'b0;
    end 
    else begin 
        case(rdState)
        1'b0:
            if(readEnVio&~readEnReg1)begin			
                rdState             <= 1'b1;
                addrbRead[31:0]     <= 32'd0;
                rd_done             <= 1'b0;
            end else begin
                rdState    <= 1'b0;
                addrbRead[31:0]  <= 32'd0;
            end
        1'b1:
            if(addrbRead[31:0] >= MAX_ADDR)begin
                rdState[0:0] <= 1'd0;
                rd_done      <= 1'b1;
            end else begin
                addrbRead[31:0] <= addrbRead[31:0] + 32'd4;
                bram_data[addrbRead[31:0]] <= doutb;
                rdState[0:0]    <= rdState[0:0];
                rd_done         <= 1'b0;
                case (addrbRead[31:0])
                    32'd0: begin
                      bram_data0 <= doutb;
                    end
                    32'd4: begin
                      bram_data1 <= doutb;
                    end
                    32'd8: begin
                      bram_data2 <= doutb;
                    end
                    32'd12: begin
                      bram_data3 <= doutb;
                    end
                    32'd16: begin
                      bram_data4 <= doutb;
                    end
                    32'd20: begin
                      bram_data5 <= doutb;
                    end
                    32'd24: begin
                      bram_data6 <= doutb;
                    end
                    32'd28: begin
                      bram_data7 <= doutb;
                    end
                    default : begin
                      bram_data0 <= bram_data0;
                      bram_data1 <= bram_data1;
                      bram_data2 <= bram_data2;
                      bram_data3 <= bram_data3;
                      bram_data4 <= bram_data4;
                      bram_data5 <= bram_data5;
                      bram_data6 <= bram_data6;
                      bram_data7 <= bram_data7;
                    end
                        
                endcase
            end
        endcase
    end
end

endmodule
